Datasheet

SAM9G20
DS60001516A-page 780  2017 Microchip Technology Inc.
44.1.15 External Bus Interface (EBI)
44.1.15.1 EBI: After reset A25 is not functionnal
After reset of the SAM9G20 device the PC10/A25 line is set into general purpose (GPIO) mode and not in peripheral mode.
This result to prevent any access to upper memory address range (0xD0000000) as the A25 EBI line is not functionnal.
Problem Fix/Workaround
According to your system memory mapping, set into your low level initialization the PC10 line in peripheral A mode.
44.2 SAM9G20 Errata - Revision B Parts
44.2.1 Analog-to-digital Converter (ADC)
44.2.1.1 ADC: Sleep Mode
If Sleep mode is activated while there is no activity (no conversion is being performed), it will take effect only after a conversion occurs.
Problem Fix/Workaround
To activate sleep mode as soon as possible, it is recommended to write successively, ADC Mode Register (SLEEP) then ADC Control
Register (START bit field); to start an analog-to-digital conversion, in order put ADC into sleep mode at the end of this conversion.
44.2.2 Boot ROM
44.2.2.1 Boot ROM: ROM Code, Internal RC Usage with SAM-BA Boot through USB
Booting from the internal RC oscillator (OSCSEL = 0) prevents using SAM-BA Boot through the USB device interface.
Problem Fix/Workaround
Use SAM-BA Boot through DBGU (or AT91SAM-ICE JTAG-ICE interface with SAM-BA GUI) if the internal RC oscillator must be used.
Boot from the 32 kHz external oscillator (OSCEL = 1) to use SAM-BA Boot through the USB.
44.2.2.2 Boot ROM: MCCK Remains Active
The ROM boot sequence is as follows:
- DataFlash on SPI0 NPCS0
- DataFlash on SPI0 NPCS1
- NAND FLash
- SDCard
-TWI
- SAM-BA Boot
MCCK is not disabled after SDCard boot program. This does not affect the TWI boot program but must be considered by any applications
using SAM-BA boot.
Problem Fix/Workaround
None.
44.2.3 Error Correction Code Controller (ECC)
44.2.3.1 ECC: 1-bit ECC per 512 Words
1-bit ECC per 512 words is not functional.
Problem Fix/Workaround
Perform the ECC computation by software.
44.2.3.2 ECC: Incomplete parity status when error in ECC parity
When a single correctable error is detected in ECC value, the error is located in ECC Parity register's field which contains a 1 in the 24
least significant bits except when the error is located in the 12th or the 24th bit. In this case these bits are always stuck at 0.
A Single correctable error is detected but it is impossible to correct it.
Problem Fix/Workaround
None.