Datasheet

SAM9G20
DS60001516A-page 78  2017 Microchip Technology Inc.
12.11 Hardware and Software Constraints
• The DataFlash, Serial Flash, NAND Flash, SDCard
(1)
, and EEPROM downloaded code size must be inferior to 16K bytes.
• The code is always downloaded from the device address 0x0000_0000 to the address 0x0000_0000 of the internal SRAM (after
remap).
• The downloaded code must be position-independent or linked at address 0x0000_0000.
• The DataFlash must be connected to NPCS0 of the SPI.
Note 1: Boot ROM does not support high capacity SDCards.
The SPI and NAND Flash drivers use several PIOs in alternate functions to communicate with devices. Care must be taken when these
PIOs are used by the application. The devices connected could be unintentionally driven at boot time, and electrical conflicts between SPI
output pins and the connected devices may appear.
To assure correct functionality, it is recommended to plug in critical devices to other pins.
Table 12-8 contains a list of pins that are driven during the boot program execution. These pins are driven during the boot sequence for a
period of less than 1 second if no correct boot program is found.
Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset
state.
Table 12-8: Pins Driven during Boot Program Execution
Peripheral Pin PIO Line
SPI0 MOSI PIOA1
SPI0 MISO PIOA0
SPI0 SPCK PIOA2
SPI0 NPCS0 PIOA3
SPI0 NPCS1 PIOC11
PIOC NANDCS PIOC14
Address Bus NAND CLE A22
Address Bus NAND ALE A21
MCI0 MCDA0 PIOA6
MCI0 MCCDA PIOA7
MCI0 MCCK PIOA8
MCI0 MCDA1 PIOA9
MCI0 MCDA2 PIOA10
MCI0 MCDA3 PIOA11
TWI TWCK PIOA24
TWI TWD PIOA23
DBGU DRXD PIOB14
DBGU DTXD PIOB15