Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 765
SAM9G20
40.12.4 ISI Timings
Timings are given assuming a capacitance load on clock and data signals as defined in Table 40-43.
Figure 40-21: ISI Timing Diagram
40.12.5 MCI Timings
Capacitance loads on data and clock are given in Table 40-46.
Table 40-43: Capacitance Load
Supply
Corner
Max
3.3V 30 pF
1.8V 20 pF
Table 40-44: ISI Timings with Peripheral Supply 3.3V
Symbol Parameter Min Max Unit
ISI
1
DATA/VSYNC/HSYNC setup time 4.5 – ns
ISI
2
DATA/VSYNC/HSYNC hold time 1.3 – ns
ISI
3
PIXCLK frequency – 66 MHz
Table 40-45: ISI Timings with Peripheral Supply 1.8V
Symbol Parameter Min Max Unit
ISI
1
DATA/VSYNC/HSYNC setup time 6.4 – ns
ISI
2
DATA/VSYNC/HSYNC hold time 2.0 – ns
ISI
3
PIXCLK frequency – 55 MHz
PIXCLK
DATA[7:0]
VSYNC
HSYNC
Valid Data
Valid Data Valid Data
ISI
1
ISI
2
ISI
3