Datasheet

SAM9G20
DS60001516A-page 754  2017 Microchip Technology Inc.
Note 1: Control is the set of following signals: SDCKE, SDCS, RAS, CAS, SDA10, BAx, DQMx, and SDWE.
2: Address is the set of A0–A9, A11–A13.
3: 133 MHz with CAS Latency = 3, 100 MHz with CAS Latency = 2.
Table 40-33: SDRAMC Characteristics
Timings Standard Parameter Supply Min Max Unit
PC100
SDRAM Controller Clock Frequency
3.3V
–100MHz
Control/Address/Data In Setup
(1)(2)
2–ns
Control/Address/Data In Hold
(1)(2)
1–ns
Data Out Access time after SDCK rising – 6 ns
Data Out change time after SDCK rising 3 – ns
PC133
SDRAM Controller Clock Frequency
3.3V
–133MHz
Control/Address/Data In Setup
(1)(2)
1.5 – ns
Control/Address/Data In Hold
(1)(2)
0.8 – ns
Data Out Access time after SDCK rising – 5.4 ns
Data Out change time after SDCK rising 3.0 – ns
Mobile SDRAM
SDRAM Controller Clock Frequency
1.8V
– 133 / 100
(3)
MHz
Control/Address/Data In Setup
(1)(2)
2.0 – ns
Control/Address/Data In Hold
(1)(2)
1.0 – ns
Data Out Access time after SDCK rising – 6.0 / 8.0
(3)
ns
Data Out change time after SDCK rising 3.0 – ns