Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 753
SAM9G20
Figure 40-5: SMC Timings - NRD Controlled Read and NWE Controlled Write
40.11 SDRAMC Timings
Timings are given assuming a capacitance load on data, control and address pads as defined in Table 40-31, as well as the SDCK pad
as defined in Table 40-32.
The SDRAM Controller satisfies the timings of standard PC100, PC133 (3.3V supply) and Mobile SDRAM (1.8V supply) that are given in
Table 40-33.
Table 40-31: Capacitance Load on data, control and address pads
I/O Supply
Corner
Max
3.3V 50 pF
1.8V 30 pF
Table 40-32: Capacitance Load on SDCK pad
I/O Supply
Corner
Max
3.3V 10 pF
1.8V 10 pF
NRD
NCS
D0–D31
NWE
A
0/A1/NBS[3:0]/A2–A25
NRD Controlled READ
with NO HOLD
NWE Controlled WRITE
with NO HOLD
NRD Controlled READ
with HOLD
NWE Controlled WRITE
with HOLD
SMC1 SMC2
SMC15
SMC21
SMC3
SMC4
SMC15
SMC19
SMC20
SMC7
SMC21
SMC16
SMC7
SMC16
SMC19
SMC21
SMC17
SMC18
SMC5 SMC5
SMC6 SMC6
SMC17
SMC18