Datasheet

SAM9G20
DS60001516A-page 750  2017 Microchip Technology Inc.
40.9 Core Power Supply POR Characteristics
40.10 EBI Timings
SMC timings are given in Max (T
A
= 85°C, VDDCORE = 0.9V) corner.
Timings are given assuming a capacitance load on data, control and address pads as defined in Table 40-26.
In the following tables t
CPMCK
is MCK period.
40.10.1 Read Timings
Table 40-25: Power-On-Reset Characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
T+
Threshold Voltage Rising Minimum Slope of +1.0V/100ms 0.5 0.7 0.89 V
V
T-
Threshold Voltage Falling 0.4 0.6 0.85 V
t
RST
Reset Time 30 70 130 µs
Table 40-26: Capacitance Load
I/O Supply
Corner
Max
3.3V 50 pF
1.8V 30 pF
Table 40-27: SMC Read Signals - NRD Controlled (READ_MODE = 1)
Symbol Parameter
Min
Unit1.8V VDDIOM Supply 3.3V VDDIOM Supply
NO HOLD SETTINGS (nrd hold = 0)
SMC
1
Data Setup before NRD High 13.0 11.4 ns
SMC
2
Data Hold after NRD High 0 0 ns
HOLD SETTINGS (nrd hold ≠ 0)
SMC
3
Data Setup before NRD High 9.6 8.0 ns
SMC
4
Data Hold after NRD High 0 0 ns
HOLD or NO HOLD SETTINGS (nrd hold ≠ 0, nrd hold = 0)
SMC
5
NBS0/A0, NBS1, NBS2/A1, NBS3,
A2–A25 Valid before NRD High
(nrd setup + nrd pulse) * t
CPMCK
- 0.4 (nrd setup + nrd pulse) * t
CPMCK
- 0.4 ns
SMC
6
NCS low before NRD High
(nrd setup + nrd pulse - ncs rd setup)
* t
CPMCK
+ 0.5
(nrd setup + nrd pulse - ncs rd setup)
* t
CPMCK
+ 0.4
ns
SMC
7
NRD Pulse Width nrd pulse * t
CPMCK
+ 0.2 nrd pulse * t
CPMCK
+ 0.1 ns