Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 73
SAM9G20
Figure 12-6: Serial Flash Download
12.6 DataFlash Boot Sequence
The DataFlash boot looks for a valid application in the SPI DataFlash memory.
SPI0 is configured in master mode to generate a SPCK at 1 MHz. DataFlash shall be connected to NPCS0 or NPCS1.
The DataFlash boot reads the DataFlash flash status register (Instruction code 0xD7). The DataFlash is considered as ready if bit 7 of the
returned status register is set.
If no DataFlash is connected or if it does not answer, DataFlash boot exits after 1000 attempts.
If the DataFlash is ready, DataFlash boot reads the first 8 words into SRAM (Instruction code “Continuous Read Array” 0x0b) and checks
if it corresponds to valid exception vectors according to the Valid Image detection algorithm.
If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after
remap. This application may be the application code or a second-level bootloader.
The DataFlash boot is configured to be compatible with the future design of the DataFlash.
End
Read the first 8 instructions (0x0b).
Decode the sixth Arm vector
Yes
Read the SerialFlash into the internal SRAM.
(code size to read in vector 6)
Restore the reset value for the peripherals.
Set the PC to 0 and perform the REMAP
to jump to the downloaded application
Send status command (0x05)
8 vectors
(except vector 6) are LDR
or Branch instruction
Yes
Start
Is status OK ?
Jump to next boot
solution
No
No