Datasheet

SAM9G20
DS60001516A-page 722  2017 Microchip Technology Inc.
39.5.3 Conversion Resolution
The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit LOWRES in the ADC Mode Register
(ADC_MR). By default, after a reset, the resolution is the highest and the DATA field in the data registers is fully used. By setting the bit
LOWRES, the ADC switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the data
registers. The two highest bits of the DATA field in the corresponding ADC_CDR and of the LDATA field in the ADC_LCDR read 0.
Moreover, when a PDC channel is connected to the ADC, 10-bit resolution sets the transfer request sizes to 16-bit. Setting the bit
LOWRES automatically switches to 8-bit data transfers. In this case, the destination buffers are optimized.
39.5.4 Conversion Results
When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register (ADC_CDR) of the current chan-
nel and in the ADC Last Converted Data Register (ADC_LCDR).
The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected PDC channel, DRDY rising
triggers a data transfer request. In any case, either EOC and DRDY can trigger an interrupt.
Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit and the EOC bit
corresponding to the last converted channel.
Figure 39-2: EOCx and DRDY Flag Behavior
If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVRE) flag is set in the Status
Register (ADC_SR).
In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun Error) in ADC_SR.
The OVRE and GOVRE flags are automatically cleared when ADC_SR is read.
Conversion Time
Read the ADC_CDRx
EOCx
DRDY
Read the ADC_LCDR
CHx
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
Write the ADC_CR
with START = 1
Conversion Time
Write the ADC_CR
with START = 1