Datasheet

SAM9G20
DS60001516A-page 72  2017 Microchip Technology Inc.
Figure 12-4: B Opcode
Unconditional instruction: 0xE for bits 31 to 28
Load PC with PC relative addressing instruction:
- Rn = Rd = PC = 0xF
-I==0
-P==1
- U offset added (U==1) or subtracted (U==0)
-W==1
12.4.2 Structure of Arm Vector 6
The Arm exception vector 6 is used to store information needed by the DataFlash boot program. This information is described below.
Figure 12-5: Structure of the Arm Vector 6
12.4.2.1 Example
An example of valid vectors follows:
00 ea000006 B 0x20
04 eafffffe B 0x04
08 ea00002f B _main
0c eafffffe B 0x0c
10 eafffffe B 0x10
14 00001234 B 0x14
<- Code size = 4660 bytes
18 eafffffe B 0x18
The size of the image to load into SRAM is contained in the location of the sixth Arm vector. Thus the user must replace this vector by the
correct size of his/her application.
12.5 Serial Flash Boot
The Serial Flash boot looks for a valid application in the SPI Serial Flash memory.
SPI0 is configured in master mode to generate a SPCK at 1 MHz. Serial Flash shall be connected to NPCS0 or NPCS1.
The Serial Flash boot reads the Serial Flash status register (Instruction code 0x05). The Serial Flash is considered as ready if bit 0 of the
returned status register is cleared.
If no Serial Flash is connected or if it does not answer, Serial Flash boot exits after 1000 attempts.
If the Serial Flash is ready, Serial Flash boot reads the first 8 words into SRAM (Instruction code “Continuos read array” 0x0b) and checks
if it corresponds to valid exception vectors according to the Valid Image detection algorithm.
If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after
remap. This application may be the application code or a second-level bootloader.
31 28 27 24 23 0
1 1 1 0 1 0 1 0 Offset (24 bits)
31 0
Size of the code to download in bytes