Datasheet

SAM9G20
DS60001516A-page 702  2017 Microchip Technology Inc.
38.4.1 ISI Control 1 Register
Name: ISI_CR1
Access: Read/Write
ISI_RST: Image Sensor Interface Reset
Write-only. Refer to bit SOFTRST in “ISI Status Register” for soft reset status.
0: No action
1: Resets the image sensor interface.
ISI_DIS: Image Sensor Disable:
0: Enable the image sensor interface.
1: Finish capturing the current frame and then shut down the module.
HSYNC_POL: Horizontal Synchronization Polarity
0: HSYNC active high
1: HSYNC active low
VSYNC_POL: Vertical sYnchronization Polarity
0: VSYNC active high
1: VSYNC active low
PIXCLK_POL: Pixel Clock Polarity
0: Data is sampled on rising edge of pixel clock
1: Data is sampled on falling edge of pixel clock
EMB_SYNC: Embedded Synchronization
0: Synchronization by HSYNC, VSYNC
1: Synchronization by embedded synchronization sequence SAV/EAV
CRC_SYNC: Embedded Synchronization
0: No CRC correction is performed on embedded synchronization
1: CRC correction is performed. if the correction is not possible, the current frame is discarded and the CRC_ERR is set in the status
register.
FRATE: Frame Rate [0..7]
0: All the frames are captured, else one frame every FRATE+1 is captured.
FULL: Full Mode is Allowed
1: Both codec and preview datapaths are working simultaneously
31 30 29 28 27 26 25 24
SFD
23 22 21 20 19 18 17 16
SLD
15 14 13 12 11 10 9 8
CODEC_ON THMASK FULL – FRATE
76543210
CRC_SYNC EMB_SYNC – PIXCLK_POL VSYNC_POL HSYNC_POL ISI_DIS ISI_RST