Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 699
SAM9G20
Example
The first FBD, stored at address 0x30000, defines the location of the first frame buffer.
Destination Address: frame buffer ID0 0x02A000
Next FBD address: 0x30010
Second FBD, stored at address 0x30010, defines the location of the second frame buffer.
Destination Address: frame buffer ID1 0x3A000
Transfer width: 32 bit
Next FBD address: 0x30000, wrapping to first FBD.
Using this technique, several frame buffers can be configured through the linked list. Figure 38-6 illustrates a typical three frame buffer
application. Frame n is mapped to frame buffer 0, frame n+1 is mapped to frame buffer 1, frame n+2 is mapped to Frame buffer 2, further
frames wrap. A codec request occurs, and the full-size 4:2:2 encoded frame is stored in a dedicated memory space.
Figure 38-6: Three Frame Buffers Application and Memory Mapping
frame n frame n+1 frame n+2frame n-1 frame n+3 frame n+4
Frame Buffer 0
Frame Buffer 1
Frame Buffer 3
4:2:2 Image
Full ROI
ISI config Space
Codec Request
Codec Done
LCD
Memory Space