Datasheet

SAM9G20
DS60001516A-page 698  2017 Microchip Technology Inc.
38.3.4.2 Color Space Conversion
This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples value do not exceed
the allowable range. The conversion matrix is defined below and is fully programmable:
Example of programmable value to convert YCrCb to RGB:
An example of programmable value to convert from YUV to RGB:
38.3.4.3 Memory Interface
Preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:5:5 format compliant with 16-bit format of the LCD controller.
In general, when converting from a color channel with more bits to one with fewer bits, formatter module discards the lower-order bits.
Example: Converting from RGB 8:8:8 to RGB 5:6:5, it discards the three LSBs from the red and blue channels, and two LSBs from the
green channel. When grayscale mode is enabled, two memory format are supported. One mode supports 2 pixels per word, and the other
mode supports 1 pixel per word.
38.3.4.4 FIFO and DMA Features
Both preview and Codec datapaths contain FIFOs, asynchronous buffers that are used to safely transfer formatted pixels from Pixel clock
domain to AHB clock domain. A video arbiter is used to manage FIFO thresholds and triggers a relevant DMA request through the AHB
master interface. Thus, depending on FIFO state, a specified length burst is asserted. Regarding AHB master interface, it supports Scatter
DMA mode through linked list operation. This mode of operation improves flexibility of image buffer location and allows the user to allocate
two or more frame buffers. The destination frame buffers are defined by a series of Frame Buffer Descriptors (FBD). Each FBD controls
the transfer of one entire frame and then optionally loads a further FBD to switch the DMA operation at another frame buffer address. The
FBD is defined by a series of two words. The first one defines the current frame buffer address, and the second defines the next FBD
memory location. This DMA transfer mode is only available for preview datapath and is configured in the ISI_PPFBD register that indicates
the memory location of the first FBD.
The primary FBD is programmed into the camera interface controller. The data to be transferred described by an FBD requires several
burst access. In the example below, the use of 2 ping-pong frame buffers is described.
Table 38-8: Grayscale Memory Mapping Configuration for 12-bit Data
GS_MODE DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0]
0 P_0[11:4] P_0[3:0], 0000 P_1[11:4] P_1[3:0], 0000
1 P_0[11:4] P_0[3:0], 0000 0 0
R
G
B
C
0
0 C
1
C
0
C
2
– C
3
–
C
0
C
4
0
YY
off
–
C
b
C
boff
–
C
r
C
roff
–
×=
R 1.164 Y 16–()⋅ 1.596 C
r
128–()⋅+=
G 1.164 Y 16–()0.813 C
r
128–()⋅– 0.392 C
b
128–()⋅–⋅=
B 1.164 Y 16–()⋅ 2.107 C
b
128–()⋅+=





RY1.596 V⋅+=
GY0.394 U⋅– 0.436 V⋅–=
BY2.032 U⋅+=




