Datasheet
SAM9G20
DS60001516A-page 690 2017 Microchip Technology Inc.
37.3 Product Dependencies
37.3.1 I/O Lines
DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceivers are controlled by the USB host con-
troller.
37.3.2 Power Management
The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a correct accuracy of ± 0.25%.
Thus the USB device peripheral receives two clocks from the Power Management Controller (PMC): the master clock MCK used to drive
the peripheral user interface (MCK domain) and the UHPCLK 48 MHz clock used to interface with the bus USB signals (Recovered 12
MHz domain).
37.3.3 Interrupt
The USB host interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling USB host interrupts requires programming the AIC before configuring the UHP.
37.4 Functional Description
Refer to the Open Host Controller Interface Specification for USB Release 1.0.a.
37.4.1 Host Controller Interface
There are two communication channels between the Host Controller and the Host Controller Driver. The first channel uses a set of oper-
ational registers located on the USB Host Controller. The Host Controller is the target for all communications on this channel. The opera-
tional registers contain control, status and list pointer registers. They are mapped in the memory mapped area. Within the operational
register set there is a pointer to a location in the processor address space named the Host Controller Communication Area (HCCA). The
HCCA is the second communication channel. The host controller is the master for all communication on this channel. The HCCA contains
the head pointers to the interrupt Endpoint Descriptor lists, the head pointer to the done queue and status information associated with
start-of-frame processing.
The basic building blocks for communication across the interface are Endpoint Descriptors (ED, 4 double words) and Transfer Descriptors
(TD, 4 or 8 double words). The host controller assigns an Endpoint Descriptor to each endpoint in the system. A queue of Transfer Descrip-
tors is linked to the Endpoint Descriptor for the specific endpoint.