Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 665
SAM9G20
writing zero or more byte values in the endpoint’s UDP_FDRx register.
5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx
register is set. An interrupt is pending while TXCOMP is being set.
6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared the second Bank
to be sent, raising TXPKTRDY in the endpoint’s UDP_CSRx register.
7. At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent
.
Figure 36-8: Data IN Transfer for Ping-pong Endpoint
Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for TX_COMP to set
TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set too long, some Data IN packets may be NACKed,
reducing the bandwidth.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
36.5.2.3 Data OUT Transaction
Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the
device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes.
• Data OUT Transaction Without Ping-pong Attributes
To perform a Data OUT transaction, using a non ping-pong endpoint:
1. The host generates a Data OUT packet.
2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller,
a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by the USB device and an ACK is auto-
matically carried out to the host.
3. The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint’s
UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set.
4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx register.
5. The microcontroller carries out data received from the endpoint’s memory to its memory. Data received is available by reading the
endpoint’s UDP_FDRx register.
6. The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx
register.
7. A new Data OUT packet can be accepted by the USB device.
Data INData IN
Read by USB Device
Read by USB Device
Bank 1
Bank 0
FIFO (DPR)
TXCOMP Flag
(UDP_CSRx)
Interrupt Cleared by Firmware
Set by USB
Device
TXPKTRDY Flag
(UDP_MCSRx)
ACK
PID
Data IN
PID
ACK
PID
Set by Firmware,
Data Payload Written in FIFO Bank 1
Cleared by USB Device,
Data Payload Fully Transmitted
Data IN
PID
USB Bus
Packets
Set by USB Device
Set by Firmware,
Data Payload Written in FIFO Bank 0
Written by
FIFO (DPR)
Microcontroller
Written by
Microcontroller
Written by
Microcontroller
Microcontroller
Load Data IN Bank 0
Microcontroller Load Data IN Bank 1
USB Device Send Bank 0
Microcontroller Load Data IN Bank 0
USB Device Send Bank 1
Interrupt Pending