Datasheet

SAM9G20
DS60001516A-page 658  2017 Microchip Technology Inc.
36. USB Device Port (UDP)
36.1 Overview
The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification.
Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM
used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read
or written by the USB device peripheral. This feature is mandatory for isochronous endpoints. Thus the device maintains the maximum
bandwidth (1 Mbyte/s) by working with endpoints with two banks of DPR.
Note 1: The Dual-Bank function provides two banks for an endpoint. This feature is used for ping-pong mode.
Suspend and resume are automatically detected by the USB device, which notifies the processor by raising an interrupt. Depending on
the product, an external signal can be used to send a wake up to the USB host controller.
36.2 Block Diagram
Figure 36-1: Block Diagram
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB
registers.
The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain (MCK) and a 48 MHz clock (UDPCK)
used by the 12 MHz domain.
Table 36-1: USB Endpoint Description
Endpoint Number Mnemonic Dual-Bank
(1)
Max. Endpoint Size Endpoint Type
0 EP0 No 64 Control/Bulk/Interrupt
1 EP1 Yes 64 Bulk/Iso/Interrupt
2 EP2 Yes 64 Bulk/Iso/Interrupt
3 EP3 No 64 Control/Bulk/Interrupt
4 EP4 Yes 512 Bulk/Iso/Interrupt
5 EP5 Yes 512 Bulk/Iso/Interrupt
Microchip Bridge
12 MHz
Suspend/Resume Logic
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Serial
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Engine
SIE
MCK
Master Clock
Domain
Dual
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RAM
FIFO
UDPCK
Recovered 12 MHz
Domain
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USB Device
Embedded
USB
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Bus
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