Datasheet

SAM9G20
DS60001516A-page 638  2017 Microchip Technology Inc.
35.5.26 EMAC Statistic Registers
These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently
enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in the network
control register. To write to these registers, bit 7 must be set in the network control register. The statistics register block contains the fol-
lowing registers.
35.5.26.1 Pause Frames Received Register
Name:EMAC_PFR
Access:Read/Write
FROK: Pause Frames Received OK
A 16-bit register counting the number of good pause frames received. A good frame has a length of 64 to 1518 (1536 if bit 8 set in network
configuration register) and has no FCS, alignment or receive symbol errors.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
FROK
76543210
FROK