Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 613
SAM9G20
35.5.2 Network Configuration Register
Name:EMAC_NCFG
Access:Read/Write
SPD: Speed
Set to 1 to indicate 100 Mbit/s operation, 0 for 10 Mbit/s. The value of this pin is reflected on the speed pin.
FD: Full Duplex
If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the
half_duplex pin.
CAF: Copy All Frames
When set to 1, all valid frames are received.
JFRAME: Jumbo Frames
Set to one to enable jumbo frames of up to 10240 bytes to be accepted.
NBC: No Broadcast
When set to 1, frames addressed to the broadcast address of all ones are not received.
MTI: Multicast Hash Enable
When set, multicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash reg-
ister.
UNI: Unicast Hash Enable
When set, unicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register.
BIG: Receive 1536 bytes frames
Setting this bit means the EMAC receives frames up to 1536 bytes in length. Normally, the EMAC would reject any frame above 1518
bytes.
CLK: MDC clock divider
Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For conformance with
802.3, MDC must not exceed 2.5MHz (MDC is only active during MDIO read and write operations).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––IRXFCSEFRHDDRFCSRLCE
15 14 13 12 11 10 9 8
RBOF PAE RTY CLK – BIG
76543210
UNI MTI NBC CAF JFRAME – FD SPD
CLK MDC
00 MCK divided by 8 (MCK up to 20 MHz)
01 MCK divided by 16 (MCK up to 40 MHz)
10 MCK divided by 32 (MCK up to 80 MHz)
11 MCK divided by 64 (MCK up to 160 MHz)