Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 611
SAM9G20
0x90 Hash Register Bottom [31:0] Register EMAC_HRB Read/Write 0x0000_0000
0x94 Hash Register Top [63:32] Register EMAC_HRT Read/Write 0x0000_0000
0x98 Specific Address 1 Bottom Register EMAC_SA1B Read/Write 0x0000_0000
0x9C Specific Address 1 Top Register EMAC_SA1T Read/Write 0x0000_0000
0xA0 Specific Address 2 Bottom Register EMAC_SA2B Read/Write 0x0000_0000
0xA4 Specific Address 2 Top Register EMAC_SA2T Read/Write 0x0000_0000
0xA8 Specific Address 3 Bottom Register EMAC_SA3B Read/Write 0x0000_0000
0xAC Specific Address 3 Top Register EMAC_SA3T Read/Write 0x0000_0000
0xB0 Specific Address 4 Bottom Register EMAC_SA4B Read/Write 0x0000_0000
0xB4 Specific Address 4 Top Register EMAC_SA4T Read/Write 0x0000_0000
0xB8 Type ID Checking Register EMAC_TID Read/Write 0x0000_0000
0xC0 User Input/Output Register EMAC_USRIO Read/Write 0x0000_0000
0xC8–0xFC Reserved – – –
Table 35-6: Register Mapping (Continued)
Offset Register Name Access Reset