Datasheet
2017 Microchip Technology Inc. DS60001516A-page 607
SAM9G20
35.3.12 PHY Maintenance
The register EMAC_MAN enables the EMAC to communicate with a PHY by means of the MDIO interface. It is used during auto-negoti-
ation to ensure that the EMAC and the PHY are configured for the same speed and duplex configuration.
The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as com-
plete when bit two is set in the network status register (about 2000 MCK cycles later when bit ten is set to zero, and bit eleven is set to
one in the network configuration register). An interrupt is generated as this bit is set. During this time, the MSB of the register is output on
the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on
MDIO.
Reading during the shift operation returns the current contents of the shift register. At the end of management operation, the bits have
shifted back to their original locations. For a read operation, the data bits are updated with data read from the PHY. It is important to write
the correct values to the register to ensure a valid PHY management frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bits[31:28] should be
written as 0x0011. For a description of MDC generation, see the network configuration register in the Section 35.5.1 Network Control Reg-
ister.
35.3.13 Media Independent Interface
The Ethernet MAC is capable of interfacing to both RMII and MII Interfaces. The RMII bit in the EMAC_USRIO register controls the inter-
face that is selected. When this bit is set, the RMII interface is selected, else the MII interface is selected.
The MII and RMII interface are capable of both 10Mb/s and 100Mb/s data rates as described in the IEEE 802.3u standard. The signals
used by the MII and RMII interfaces are described in Table 35-5.
The intent of the RMII is to provide a reduced pin count alternative to the IEEE 802.3u MII. It uses 2 bits for transmit (ETX0 and ETX1)
and two bits for receive (ERX0 and ERX1). There is a Transmit Enable (ETXEN), a Receive Error (ERXER), a Carrier Sense (ECRS_DV),
and a 50 MHz Reference Clock (ETXCK_EREFCK) for 100Mb/s data rate.
35.3.13.1 RMII Transmit and Receive Operation
The same signals are used internally for both the RMII and the MII operations. The RMII maps these signals in a more pin-efficient manner.
The transmit and receive bits are converted from a 4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. The
carrier sense and data valid signals are combined into the ECRSDV signal. This signal contains information on carrier sense, FIFO status,
and validity of the data. Transmit error bit (ETXER) and collision detect (ECOL) are not used in RMII mode.
Table 35-5: Pin Configuration
Pin Name MII RMII
ETXCK_EREFCK ETXCK: Transmit Clock EREFCK: Reference Clock
ECRS ECRS: Carrier Sense
ECOL ECOL: Collision Detect
ERXDV ERXDV: Data Valid ECRSDV: Carrier Sense/Data Valid
ERX0–ERX3 ERX0–ERX3: 4-bit Receive Data ERX0–ERX1: 2-bit Receive Data
ERXER ERXER: Receive Error ERXER: Receive Error
ERXCK ERXCK: Receive Clock
ETXEN ETXEN: Transmit Enable ETXEN: Transmit Enable
ETX0–ETX3 ETX0–ETX3: 4-bit Transmit Data ETX0–ETX1: 2-bit Transmit Data
ETXER ETXER: Transmit Error