Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 605
SAM9G20
The enable bit for jumbo frames in the network configuration register allows the EMAC to receive jumbo frames of up to 10240 bytes in
size. This operation does not form part of the IEEE802.3 specification and is disabled by default. When jumbo frames are enabled, frames
received with a frame size greater than 10240 bytes are discarded.
35.3.6 Address Checking Block
The address checking (or filter) block indicates to the DMA block which receive frames should be copied to memory. Whether a frame is
copied depends on what is enabled in the network configuration register, the state of the external match pin, the contents of the specific
address and hash registers and the frame’s destination address. In this implementation of the EMAC, the frame’s source address is not
checked. Provided that bit 18 of the Network Configuration register is not set, a frame is not copied to memory if the EMAC is transmitting
in half duplex mode at the time a destination address is received. If bit 18 of the Network Configuration register is set, frames can be
received while transmitting in half-duplex mode.
Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an Ethernet frame make up the
destination address. The first bit of the destination address, the LSB of the first byte of the frame, is the group/individual bit: this is One for
multicast addresses and Zero for unicast. The All Ones address is the broadcast address, and a special case of multicast.
The EMAC supports recognition of four specific addresses. Each specific address requires two registers, specific address register bottom
and specific address register top. Specific address register bottom stores the first four bytes of the destination address and specific
address register top contains the last two bytes. The addresses stored can be specific, group, local or universal.
The destination address of received frames is compared against the data stored in the specific address registers once they have been
activated. The addresses are deactivated at reset or when their corresponding specific address register bottom is written. They are acti-
vated when specific address register top is written. If a receive frame address matches an active address, the frame is copied to memory.
The following example illustrates the use of the address match registers for a MAC address of 21:43:65:87:A9:CB.
Preamble 55
SFD D5
DA (Octet0 - LSB) 21
DA(Octet 1) 43
DA(Octet 2) 65
DA(Octet 3) 87
DA(Octet 4) A9
DA (Octet5 - MSB) CB
SA (LSB) 00
SA 00
SA 00
SA 00
SA 00
SA (MSB) 43
SA (LSB) 21
The sequence above shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom as shown. For a suc-
cessful match to specific address 1, the following address matching registers must be set up:
• Base address + 0x98 0x87654321 (Bottom)
• Base address + 0x9C 0x0000CBA9 (Top)
And for a successful match to the Type ID register, the following should be set up:
• Base address + 0xB8 0x00004321
35.3.7 Broadcast Address
The broadcast address of 0xFFFFFFFFFFFF is recognized if the ‘no broadcast’ bit in the network configuration register is zero.