Datasheet

SAM9G20
DS60001516A-page 604  2017 Microchip Technology Inc.
35.3.3 Transmit Block
This block transmits frames in accordance with the Ethernet IEEE 802.3 CSMA/CD protocol. Frame assembly starts by adding preamble
and the start frame delimiter. Data is taken from the transmit FIFO a word at a time. Data is transmitted least significant nibble first. If nec-
essary, padding is added to increase the frame length to 60 bytes. CRC is calculated as a 32-bit polynomial. This is inverted and appended
to the end of the frame, taking the frame length to a minimum of 64 bytes. If the No CRC bit is set in the second word of the last buffer
descriptor of a transmit frame, neither pad nor CRC are appended.
In full-duplex mode, frames are transmitted immediately. Back-to-back frames are transmitted at least 96 bit times apart to guarantee the
interframe gap.
In half-duplex mode, the transmitter checks carrier sense. If asserted, it waits for it to de-assert and then starts transmission after the inter-
frame gap of 96 bit times. If the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken
from the data register and then retry transmission after the back off time has elapsed.
The back-off time is based on an XOR of the 10 least significant bits of the data coming from the transmit FIFO and a 10-bit pseudo random
number generator. The number of bits used depends on the number of collisions seen. After the first collision, 1 bit is used, after the second
2, and so on up to 10. Above 10, all 10 bits are used. An error is indicated and no further attempts are made if 16 attempts cause collisions.
If transmit DMA underruns, bad CRC is automatically appended using the same mechanism as jam insertion and the tx_er signal is
asserted. For a properly configured system, this should never happen.
If the back pressure bit is set in the network control register in half duplex mode, the transmit block transmits 64 bits of data, which can
consist of 16 nibbles of 1011 or in bit-rate mode 64 1s, whenever it sees an incoming frame to force a collision. This provides a way of
implementing flow control in half-duplex mode.
35.3.4 Pause Frame Support
The start of an 802.3 pause frame is as follows:
The network configuration register contains a receive pause enable bit (13). If a valid pause frame is received, the pause time register is
updated with the frame’s pause time, regardless of its current contents and regardless of the state of the configuration register bit 13. An
interrupt (12) is triggered when a pause frame is received, assuming it is enabled in the interrupt mask register. If bit 13 is set in the network
configuration register and the value of the pause time register is non-zero, no new frame is transmitted until the pause time register has
decremented to zero.
The loading of a new pause time, and hence the pausing of transmission, only occurs when the EMAC is configured for full-duplex oper-
ation. If the EMAC is configured for half-duplex, there is no transmission pause, but the pause frame received interrupt is still triggered.
A valid pause frame is defined as having a destination address that matches either the address stored in specific address register 1 or
matches 0x0180C2000001 and has the MAC control frame type ID of 0x8808 and the pause opcode of 0x0001. Pause frames that have
FCS or other errors are treated as invalid and are discarded. Valid pause frames received increment the Pause Frame Received statistic
register.
The pause time register decrements every 512 bit times (i.e., 128 rx_clks in nibble mode) once transmission has stopped. For test
purposes, the register decrements every rx_clk cycle once transmission has stopped if bit 12 (retry test) is set in the network configu-
ration register. If the pause enable bit (13) is not set in the network configuration register, then the decrementing occurs regardless of
whether transmission has stopped or not.
An interrupt (13) is asserted whenever the pause time register decrements to zero (assuming it is enabled in the interrupt mask register).
35.3.5 Receive Block
The receive block checks for valid preamble, FCS, alignment and length, presents received frames to the DMA block and stores the frames
destination address for use by the address checking block. If, during frame reception, the frame is found to be too long or rx_er is asserted,
a bad frame indication is sent to the DMA block. The DMA block then ceases sending data to memory. At the end of frame reception, the
receive block indicates to the DMA block whether the frame is good or bad. The DMA block recovers the current receive buffer if the frame
was bad. The receive block signals the register block to increment the alignment error, the CRC (FCS) error, the short frame, long frame,
jabber error, the receive symbol error statistics and the length field mismatch statistics.
Table 35-3: Start of an 802.3 Pause Frame
Destination Address Source Address
Type
(Mac Control Frame) Pause Opcode Pause Time
0x0180C2000001 6 bytes 0x8808 0x0001 2 bytes