Datasheet

SAM9G20
DS60001516A-page 602  2017 Microchip Technology Inc.
To receive frames, the buffer descriptors must be initialized by writing an appropriate address to bits 31 to 2 in the first word of each list
entry. Bit zero must be written with zero. Bit one is the wrap bit and indicates the last entry in the list.
The start location of the receive buffer descriptor list must be written to the receive buffer queue pointer register before setting the receive
enable bit in the network control register to enable receive. As soon as the receive block starts writing received frame data to the receive
FIFO, the receive buffer manager reads the first receive buffer location pointed to by the receive buffer queue pointer register.
If the filter block then indicates that the frame should be copied to memory, the receive data DMA operation starts writing data into the
receive buffer. If an error occurs, the buffer is recovered. If the current buffer pointer has its wrap bit set or is the 1024
th
descriptor, the next
receive buffer location is read from the beginning of the receive descriptor list. Otherwise, the next receive buffer location is read from the
next word in memory.
There is an 11-bit counter to count out the 2048 word locations of a maximum length, receive buffer descriptor list. This is added with the
value originally written to the receive buffer queue pointer register to produce a pointer into the list. A read of the receive buffer queue
pointer register returns the pointer value, which is the queue entry currently being accessed. The counter is reset after receive status is
written to a descriptor that has its wrap bit set or rolls over to zero after 1024 descriptors have been accessed. The value written to the
receive buffer pointer register may be any word-aligned address, provided that there are at least 2048 word locations available between
the pointer and the top of the memory.
Section 3.6 of the AMBA 2.0 specification states that bursts should not cross 1K boundaries. As receive buffer manager writes are bursts
of two words, to ensure that this does not occur, it is best to write the pointer register with the least three significant bits set to zero. As
receive buffers are used, the receive buffer manager sets bit zero of the first word of the descriptor to indicate used. If a receive error is
detected the receive buffer currently being written is recovered. Previous buffers are not recovered. Software should search through the
used bits in the buffer descriptors to find out how many frames have been received. It should be checking the start-of-frame and end-of-
frame bits, and not rely on the value returned by the receive buffer queue pointer register which changes continuously as more buffers are
used.
For CRC errored frames, excessive length frames or length field mismatched frames, all of which are counted in the statistics registers, it
is possible that a frame fragment might be stored in a sequence of receive buffers. Software can detect this by looking for start of frame
bit set in a buffer following a buffer with no end of frame bit set.
For a properly working Ethernet system, there should be no excessively long frames or frames greater than 128 bytes with CRC/FCS
errors. Collision fragments are less than 128 bytes long. Therefore, it is a rare occurrence to find a frame fragment in a receive buffer.
If bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot
be used again until software has processed the frame and cleared bit zero. In this case, the DMA block sets the buffer not available bit in
the receive status register and triggers an interrupt.
If bit zero is set when the receive buffer manager reads the location of the receive buffer and a frame is being received, the frame is dis-
carded and the receive resource error statistics register is incremented.
A receive overrun condition occurs when bus was not granted in time or because HRESP was not OK (bus error). In a receive overrun
condition, the receive overrun interrupt is asserted and the buffer currently being written is recovered. The next frame received with an
address that is recognized reuses the buffer.
If bit 17 of the network configuration register is set, the FCS of received frames shall not be copied to memory. The frame length indicated
in the receive status field shall be reduced by four bytes in this case.
35.3.2.3 Transmit Buffer
Frames to be transmitted are stored in one or more transmit buffers. Transmit buffers can be between 0 and 2047 bytes long, so it is pos-
sible to transmit frames longer than the maximum length specified in IEEE Standard 802.3. Zero length buffers are allowed. The maximum
number of buffers permitted for each transmit frame is 128.
The start location for each transmit buffer is stored in memory in a list of transmit buffer descriptors at a location pointed
to by the transmit
buf
fer qu
eue pointer register. Each list entry consists of two words, the first being the byte address of the transmit buffer and the second
containing the transmit control and status. Frames can be transmitted with or without automatic CRC generation. If CRC is automatically
generated, pad is also automatically generated to take frames to a minimum length of 64 bytes. Table 35-2 defines an entry in the transmit
buffer descriptor list. To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address to bits 31 to 0 in
the first word of each list entry. The second transmit buffer descriptor is initialized with control information that indicates the length of the
buffer, whether or not it is to be transmitted with CRC and whether the buffer is the last buffer in the frame.
After transmission, the control bits are written back to the second word of the first buffer along with the “used” bit and other status infor-
mation. Bit 31 is the “used” bit which must be zero when the control word is read if transmission is to happen. It is written to one when a
frame has been transmitted. Bits 27, 28 and 29 indicate various transmit error conditions. Bit 30 is the “wrap” bit which can be set for any
buffer within a frame. If no wrap bit is encountered after 1024 descriptors, the queue pointer rolls over to the start in a similar fashion to
the receive queue.