Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 601
SAM9G20
35.3.2.2 Receive Buffers
Received frames, including CRC/FCS optionally, are written to receive buffers stored in memory. Each receive buffer is 128 bytes long.
The start location for each receive buffer is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive
buffer queue pointer register. The receive buffer start location is a word address. For the first buffer of a frame, the start location can be
offset by up to three bytes depending on the value written to bits 14 and 15 of the network configuration register. If the start location of the
buffer is offset the available length of the first buffer of a frame is reduced by the corresponding number of bytes.
Each list entry consists of two words, the first being the address of the receive buffer and the second being the receive status. If the length
of a receive frame exceeds the buffer length, the status word for the used buffer is written with zeroes except for the “start of frame” bit
and the offset bits, if appropriate. Bit zero of the address field is written to one to show the buffer has been used. The receive buffer man-
ager then reads the location of the next receive buffer and fills that with receive frame data. The final buffer descriptor status word contains
the complete frame status. Refer to the table below for details of the receive buffer descriptor list.
Table 35-1: Receive Buffer Descriptor Entry
Bit Function
Word 0
31:2 Address of beginning of buffer
1 Wrap - marks last descriptor in receive buffer descriptor list.
0
Ownership - needs to be zero for the EMAC to write data to the receive buffer. The EMAC sets this to one once it has
successfully written a frame to memory.
Software has to clear this bit before the buffer can be used again.
Word 1
31 Global all ones broadcast address detected
30 Multicast hash match
29 Unicast hash match
28 External address match
27 Reserved for future use
26 Specific address register 1 match
25 Specific address register 2 match
24 Specific address register 3 match
23 Specific address register 4 match
22 Type ID match
21 VLAN tag detected (i.e., type id of 0x8100)
20 Priority tag detected (i.e., type id of 0x8100 and null VLAN identifier)
19:17 VLAN priority (only valid if bit 21 is set)
16 Concatenation format indicator (CFI) bit (only valid if bit 21 is set)
15
End of frame - when set the buffer contains the end of a frame. If end of frame is not set, then the only other valid status are
bits 12, 13 and 14.
14
Start of frame - when set the buffer contains the start of a frame. If both bits 15 and 14 are set, then the buffer contains a
whole frame.
13:12
Receive buffer offset - indicates the number of bytes by which the data in the first buffer is offset from the word address.
Updated with the current values of the network configuration register. If jumbo frame mode is enabled through bit 3 of the
network configuration register, then bits 13:12 of the receive buffer descriptor entry are used to indicate bits 13:12 of the
frame length.
11:0 Length of frame including FCS (if selected). Bits 13:12 are also used if jumbo frame mode is selected.