Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 597
SAM9G20
34.9.13 MCI Interrupt Disable Register
Name: MCI_IDR
Access: Write-only
CMDRDY: Command Ready Interrupt Disable
RXRDY: Receiver Ready Interrupt Disable
TXRDY: Transmit Ready Interrupt Disable
BLKE: Data Block Ended Interrupt Disable
DTIP: Data Transfer in Progress Interrupt Disable
NOTBUSY: Data Not Busy Interrupt Disable
ENDRX: End of Receive Buffer Interrupt Disable
ENDTX: End of Transmit Buffer Interrupt Disable
SDIOIRQA: SDIO Interrupt for Slot A Interrupt Disable
SDIOIRQB: SDIO Interrupt for Slot B Interrupt Disable
RXBUFF: Receive Buffer Full Interrupt Disable
TXBUFE: Transmit Buffer Empty Interrupt Disable
RINDE: Response Index Error Interrupt Disable
RDIRE: Response Direction Error Interrupt Disable
RCRCE: Response CRC Error Interrupt Disable
RENDE: Response End Bit Error Interrupt Disable
RTOE: Response Time-out Error Interrupt Disable
DCRCE: Data CRC Error Interrupt Disable
DTOE: Data Time-out Error Interrupt Disable
OVRE: Overrun Interrupt Disable
UNRE: UnderRun Interrupt Disable
0: No effect.
1: Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
UNREOVRE––––––
23 22 21 20 19 18 17 16
– DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFE RXBUFF – – - - SDIOIRQB SDIOIRQA
76543210
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY