Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 593
SAM9G20
34.9.11 MCI Status Register
Name: MCI_SR
Access: Read-only
CMDRDY: Command Ready
0: A command is in progress.
1: The last command has been sent. Cleared when writing in the MCI_CMDR.
RXRDY: Receiver Ready
0: Data has not yet been received since the last read of MCI_RDR.
1: Data has been received since the last read of MCI_RDR.
TXRDY: Transmit Ready
0: The last data written in MCI_TDR has not yet been transferred in the Shift Register.
1: The last data written in MCI_TDR has been transferred in the Shift Register.
BLKE: Data Block Ended
This flag must be used only for Write Operations.
0: A data block transfer is not yet finished. Cleared when reading the MCI_SR.
1: A data block transfer has ended, including the CRC16 Status transmission.
In PDC mode (PDCMODE = 1), the flag is set when the CRC Status of the last block has been transmitted (TXBUFE already set).
Otherwise (PDCMODE = 0), the flag is set for each transmitted CRC Status.
Refer to the MMC or SD Specification for more details concerning the CRC Status.
DTIP: Data Transfer in Progress
0: No data transfer in progress.
1: The current data transfer is still in progress, including CRC16 calculation. Cleared at the end of the CRC16 calculation.
NOTBUSY: MCI Not Busy
This flag must be used only for Write Operations.
A block write operation uses a simple busy signalling of the write operation duration on the data (DAT0) line: during a data transfer block,
if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line (DAT0) to LOW. The card
stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free.
The NOTBUSY flag allows to deal with these different states.
0: The MCI is not ready for new data transfer. Cleared at the end of the card response.
1: The MCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free internal data
receive buffer of the card.
Refer to the MMC or SD Specification for more details concerning the busy behavior.
ENDRX: End of RX Buffer
0: The Receive Counter Register has not reached 0 since the last write in MCI_RCR or MCI_RNCR.
1: The Receive Counter Register has reached 0 since the last write in MCI_RCR or MCI_RNCR.
31 30 29 28 27 26 25 24
UNREOVRE––––––
23 22 21 20 19 18 17 16
– DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFE RXBUFF – – - - SDIOIRQB SDIOIRQA
76543210
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY