Datasheet

SAM9G20
DS60001516A-page 582  2017 Microchip Technology Inc.
34.9.2 MCI Mode Register
Name: MCI_MR
Access: Read/Write
CLKDIV: Clock Divider
Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)).
PWSDIV: Power Saving Divider
Multimedia Card Interface clock is divided by 2
(PWSDIV)
+ 1 when entering Power Saving Mode.
Warning:
This value must be different from 0 before enabling the Power Save Mode in the MCI_CR (MCI_PWSEN bit).
RDPROOF Read Proof Enable
Enabling Read Proof allows to stop the MCI Clock during read access if the internal FIFO is full. This will guarantee data integrity, not
bandwidth.
0: Disables Read Proof.
1: Enables Read Proof.
WRPROOF Write Proof Enable
Enabling Write Proof allows to stop the MCI Clock during write access if the internal FIFO is full. This will guarantee data integrity, not
bandwidth.
0: Disables Write Proof.
1: Enables Write Proof.
PDCFBYTE: PDC Force Byte Transfer
Enabling PDC Force Byte Transfer allows the PDC to manage with internal byte transfers, so that transfer of blocks with a size different
from modulo 4 can be supported.
Warning:
BLKLEN value depends on PDCFBYTE.
0: Disables PDC Force Byte Transfer. PDC type of transfer are in words.
1: Enables PDC Force Byte Transfer. PDC type of transfer are in bytes.
PDCPADV: PDC Padding Value
0: 0x00 value is used when padding data in write transfer (not only PDC transfer).
1: 0xFF value is used when padding data in write transfer (not only PDC transfer).
PDCMODE: PDC-oriented Mode
0: Disables PDC transfer
1: Enables PDC transfer. In this case, UNRE and OVRE flags in the MCI Mode Register (MCI_SR) are deactivated after the PDC transfer
has been completed.
31 30 29 28 27 26 25 24
BLKLEN
23 22 21 20 19 18 17 16
BLKLEN
15 14 13 12 11 10 9 8
PDCMODE PDCPADV PDCFBYTE WRPROOF RDPROOF PWSDIV
76543210
CLKDIV