Datasheet

SAM9G20
DS60001516A-page 580  2017 Microchip Technology Inc.
34.9 MultiMedia Card Interface (MCI) User Interface
Note 1: The response register can be read by N accesses at the same MCI_RSPR or at consecutive addresses (0x20 to 0x2C).
N depends on the size of the response.
Table 34-6: Register Mapping
Offset Register Name Access Reset
0x00 Control Register MCI_CR Write-only –
0x04 Mode Register MCI_MR Read/Write 0x0
0x08 Data Timeout Register MCI_DTOR Read/Write 0x0
0x0C SD/SDIO Card Register MCI_SDCR Read/Write 0x0
0x10 Argument Register MCI_ARGR Read/Write 0x0
0x14 Command Register MCI_CMDR Write-only –
0x18 Block Register MCI_BLKR Read/Write 0x0
0x1C Reserved – – –
0x20 Response Register
(1)
MCI_RSPR Read-only 0x0
0x24 Response Register
(1)
MCI_RSPR Read-only 0x0
0x28 Response Register
(1)
MCI_RSPR Read-only 0x0
0x2C Response Register
(1)
MCI_RSPR Read-only 0x0
0x30 Receive Data Register MCI_RDR Read-only 0x0
0x34 Transmit Data Register MCI_TDR Write-only –
0x38–0x3C Reserved – – –
0x40 Status Register MCI_SR Read-only 0xC0E5
0x44 Interrupt Enable Register MCI_IER Write-only –
0x48 Interrupt Disable Register MCI_IDR Write-only –
0x4C Interrupt Mask Register MCI_IMR Read-only 0x0
0x50–0xFC Reserved – – –
0x100–0x124 Reserved for the PDC – – –