Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 57
SAM9G20
NTRST (optional in IEEE Standard 1149.1) is a Test-Reset input which is mandatory in Arm cores and used to reset the debug logic. On
Microchip Arm926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset
the debug logic with the NTRST pin assertion during 2.5 MCK periods.
TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and not by the tested
device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on Arm926EJ-S cores is 1/6th the clock of the CPU. This
gives 5.45 kHz maximum initial JTAG clock rate for an Arm9E
™
running from the 32.768 kHz slow clock.
RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators. From some ICE Inter-
face probes, this return signal can be used to synchronize the TCK clock and take not care about the given ratio between the ICE Interface
clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode.
11.5.4 Debug Unit
The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal
means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller
channels permits packet handling of these tasks with processor time reduced to a minimum.
The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the
activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface.
A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration.
The SAM9G20 Debug Unit Chip ID value is 0x0199 05A1 on 32-bit width.
For further details on the Debug Unit, see Section 27. “Debug Unit (DBGU)”.
11.5.5 IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented.
In ICE debug mode, the Arm processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE
1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
11.5.5.1 JTAG Boundary-scan Register
The Boundary-scan Register (BSR) contains 308 bits that correspond to active pins and associated control signals.
Each SAM9G20 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad.
The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad.
Table 11-2: SAM9G20 JTAG Boundary Scan Register
Bit Number Pin Name Pin Type Associated BSR Cells
307
A0 IN/OUT
CONTROL
306 INPUT/OUTPUT
305
A1 IN/OUT
CONTROL
304 INPUT/OUTPUT
303
A10 IN/OUT
CONTROL
302 INPUT/OUTPUT
301
A11 IN/OUT
CONTROL
300 INPUT/OUTPUT
299
A12 IN/OUT
CONTROL
298 INPUT/OUTPUT
297
A13 IN/OUT
CONTROL
296 INPUT/OUTPUT