Datasheet

SAM9G20
DS60001516A-page 566  2017 Microchip Technology Inc.
34. MultiMedia Card Interface (MCI)
34.1 Overview
The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V3.11, the SDIO Specification V1.1 and the SD
Memory Card Specification V1.0.
The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically
handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor
overhead.
The MCI supports stream, block and multi-block data read and write, and is compatible with the Peripheral DMA Controller (PDC) chan-
nels, minimizing processor intervention for large buffer transfers.
The MCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 2 slot(s). Each slot may be used to interface
with a MultiMediaCard bus (up to 30 Cards) or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A
bit field in the SD Card Register performs this selection.
The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the MultiMedia
Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use).
The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are
the initialization process and the bus topology.
34.2 Block Diagram
Figure 34-1: Block Diagram
Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to
MCIx_CDB,MCDAy to MCIx_DAy, MCDBy to MCIx_DBy.
MCI Interface
Interrupt Control
PIO
PDC
APB Bridge
PMC
MCK
MCI Interrupt
MCCK
(1)
MCCDA
(1)
MCDA0
(1)
MCDA1
(1)
MCDA2
(1)
MCDA3
(1)
MCCDB
(1)
MCDB0
(1)
MCDB1
(1)
MCDB2
(1)
MCDB3
(1)
APB