Datasheet

SAM9G20
DS60001516A-page 56  2017 Microchip Technology Inc.
11.4 Debug and Test Pin Description
11.5 Functional Description
11.5.1 Test Pin
One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure
normal operating conditions. Other values associated with this pin are reserved for manufacturing test.
11.5.2 EmbeddedICE
The Arm9EJ-S EmbeddedICE-RT
™
is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug
support is implemented using an Arm9EJ-S core embedded within the Arm926EJ-S. The internal state of the Arm926EJ-S is examined
through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus.
Therefore, when in debug state, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the
Arm9EJ-S registers. This data can be serially shifted out without affecting the rest of the system.
There are two scan chains inside the Arm9EJ-S processor which support testing, debugging, and programming of the EmbeddedICE-RT.
The scan chains are controlled by the ICE/JTAG port.
EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset
must be performed after JTAGSEL is changed.
For further details on the EmbeddedICE-RT, see the Arm document:
Arm9EJ-S Technical Reference Manual (DDI 0222A).
11.5.3 JTAG Signal Description
TMS is the Test Mode Select input which controls the transitions of the test interface state machine.
TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data
registers).
TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment controlling the test. It
carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test
circuit.
Table 11-1: Debug and Test Pin List
Pin Name Function Type Active Level
Reset/Test
NRST Microprocessor Reset Input/Output Low
TST Test Mode Select Input High
ICE and JTAG
NTRST Test Reset Signal Input Low
TCK Test Clock Input –
TDI Test Data In Input –
TDO Test Data Out Output –
TMS Test Mode Select Input –
RTCK Returned Test Clock Output –
JTAGSEL JTAG Selection Input –
Debug Unit
DRXD Debug Receive Data Input –
DTXD Debug Transmit Data Output –