Datasheet

SAM9G20
DS60001516A-page 536  2017 Microchip Technology Inc.
33.3 Pin Name List
33.4 Product Dependencies
33.4.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the
PIO controllers to assign the TC pins to their peripheral functions.
33.4.2 Power Management
The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the
Timer Counter clock.
33.4.3 Interrupt
The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TC interrupt requires programming the
AIC before configuring the TC.
33.5 Functional Description
33.5.1 TC Description
The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in
Table 33-4.
33.5.2 16-bit Counter
Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock.
When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Reg-
ister) is set.
The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a
trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock.
33.5.3 Clock Selection
At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be con-
nected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 33-2.
Each channel can independently select an internal or external clock source for its counter:
• Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5
• External clock signals: XC0, XC1 or XC2
This selection is made by the TCCLKS bits in the TC Channel Mode Register.
The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock.
The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines
this signal (none, XC0, XC1, XC2). See Figure 33-3.
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The
external clock frequency must be at least 2.5 times lower than the master clock
Table 33-3: TC pin list
Pin Name Description Type
TCLK0–TCLK2 External Clock Input Input
TIOA0–TIOA2 I/O Line A I/O
TIOB0–TIOB2 I/O Line B I/O