Datasheet

SAM9G20
DS60001516A-page 512  2017 Microchip Technology Inc.
32.8.3 SSC Receive Clock Mode Register
Name:SSC_RCMR
Access:Read/Write
CKS: Receive Clock Selection
CKO: Receive Clock Output Mode Selection
CKI: Receive Clock Inversion
0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted
out on Receive Clock rising edge.
1: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out
on Receive Clock falling edge.
CKI affects only the Receive Clock and not the output clock signal.
CKG: Receive Clock Gating Selection
31 30 29 28 27 26 25 24
PERIOD
23 22 21 20 19 18 17 16
STTDLY
15 14 13 12 11 10 9 8
– – – STOP START
76543210
CKG CKI CKO CKS
CKS Selected Receive Clock
0x0
Divided Clock
0x1
TK Clock signal
0x2
RK pin
0x3
Reserved
CKO Receive Clock Output Mode RK pin
0x0 None Input-only
0x1 Continuous Receive Clock Output
0x2 Receive Clock only during data transfers Output
0x3–0x7 Reserved
CKG Receive Clock Gating
0x0
None, continuous clock
0x1
Receive Clock enabled only if RF Low
0x2
Receive Clock enabled only if RF High
0x3
Reserved