Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 511
SAM9G20
32.8.2 SSC Clock Mode Register
Name:SSC_CMR
Access:Read/Write
DIV: Clock Divider
0: The Clock Divider is not active.
Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit
rate is MCK/2 x 4095 = MCK/8190.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
–––– DIV
76543210
DIV