Datasheet
2017 Microchip Technology Inc. DS60001516A-page 51
SAM9G20
Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits,
if set, mark the associated half-lines as dirty. If the cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used
to decide whether all, half or none is written back to memory.
DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in Arm926EJ-
S TRM).
The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU trans-
lation tables.
The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction
or cleaning of dirty cache lines.
The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected
as their configuration is set in each section by the page descriptor in the MMU translation table.
10.6.2.2 Write Buffer
The Arm926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes
to a bufferable region, write-through region and write-back region. It also allows to avoid stalling the processor when writes to external
memory are performed. When a store occurs, data is written to the write buffer at core speed (high speed). The write buffer then completes
the store to external memory at bus speed (typically slower than the core speed). During this time, the Arm9EJ-S processor can preform
other tasks.
DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each section and page
descriptor within the MMU translation tables.
10.6.2.3 Write-though Operation
When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer which transfers it to external
memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to exter-
nal memory.
10.6.2.4 Write-back Operation
When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the
external memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to exter-
nal memory.
10.7 Bus Interface Unit
The Arm926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB,
based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is
achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible
system architecture.
The multi-master bus architecture has a number of benefits:
• It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture.
• Each AHB layer becomes simple because it only has one master, so no arbitration or master-to-slave muxing is required. AHB lay-
ers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transac-
tions.
• The arbitration becomes effective when more than one master wants to access the same slave simultaneously.
10.7.1 Supported Transfers
The Arm926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any Arm9EJ-S core
request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that the Microchip bus is AHB-Lite protocol compliant,
hence it does not support split and retry requests.