Datasheet

SAM9G20
DS60001516A-page 504  2017 Microchip Technology Inc.
32.6.5 Frame Sync
The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization sig-
nals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode
Register (SSC_TFMR) are used to select the required waveform.
• Programmable low or high levels during data transfer are supported.
• Programmable high levels before the start of data transfers or toggling are also supported.
If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse,
from 1 bit time up to 256 bit time.
The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD)
field in SSC_RCMR and SSC_TCMR.
32.6.5.1 Frame Sync Data
Frame Sync Data transmits or receives a specific tag during the Frame Sync signal.
During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the
transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame
Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 16.
Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event
and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift
Register.
The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is
set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal
transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register, then shifted
out.
32.6.5.2 Frame Sync Edge Detection
The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags
RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF).
32.6.6 Receive Compare Modes
Figure 32-12: Receive Compare Modes
32.6.6.1 Compare Functions
Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but
with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare
0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0
pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start
a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with
the bit (STOP) in SSC_RCMR.
CMP0
CMP3
CMP2
CMP1
Ignored
B0
B2
B1
Start
RK
RD
(Input)
FSLEN
Up to 16 Bits
(4 in This Example)
STDLY DATLEN