Datasheet

SAM9G20
DS60001516A-page 500  2017 Microchip Technology Inc.
Figure 32-6: Transmitter Clock Management
32.6.1.3 Receiver Clock Management
The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive
Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the
CKI bits in SSC_RCMR.
The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the
SSC_RCMR. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR to select RK pin (CKS
field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results.
Figure 32-7: Receiver Clock Management
32.6.1.4 Serial Clock Ratio Considerations
The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows
the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is:
- Master Clock divided by 2 if Receiver Frame Synchro is input
- Master Clock divided by 3 if Receiver Frame Synchro is output
TK (pin)
Receiver
Clock
Divider
Clock
CKS
CKO
Data Transfer
CKI
CKG
Transmitter
Clock
Clock
Output
MUX
Tri-state
Controller
Tri-state
Controller
INV
MUX
RK (pin)
Transmitter
Clock
Divider
Clock
CKS
CKO
Data Transfer
CKI
CKG
Receiver
Clock
Clock
Output
MUX
Tri-state
Controller
Tri-state
Controller
INV
MUX