Datasheet

SAM9G20
DS60001516A-page 498 2017 Microchip Technology Inc.
Figure 32-3: SSC Functional Block Diagram
32.6.1 Clock Management
The transmitter clock can be generated by:
an external clock received on the TK I/O pad
the receiver clock
the internal clock divider
The receiver clock can be generated by:
an external clock received on the RK I/O pad
the transmitter clock
the internal clock divider
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock
on the RK I/O pad.
This allows the SSC to support many Master and Slave Mode data transfers.
Interrupt Control
AIC
User
Interface
APB
MCK
Receive Clock
Controller
Start
Selector
TX Clock
RK Input
RF
TF
Clock Output
Controller
Frame Sync
Controller
Transmit Clock
Controller
Transmit Shift Register
Start
Selector
Transmit Sync
Holding Register
Transmit Holding
Register
Load Shift
RX clock
TX clock
TK Input
TF
TX PDC
RF
RD
RF
RK
Clock Output
Controller
Frame Sync
Controller
Receive Shift Register
Receive Sync
Holding Register
Receive Holding
Register
Load Shift
TD
TF
TK
RX Clock
RX PDC
Receiver
PDC
Transmitter
Clock
Divider