Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 49
SAM9G20
10.5 Memory Management Unit (MMU)
The Arm926EJ-S processor implements an enhanced Arm architecture v5 MMU to provide virtual memory features required by operating
systems like Symbian OS
®
, Windows CE, and Linux. These virtual memory features are memory access permission controls and virtual
to physical address translations.
The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Exten-
sion) using the value in CP15 register13. The MMU translates modified virtual addresses to physical addresses by using a single, two-
level page table set stored in physical memory. Each entry in the set contains the access permissions and the physical address that cor-
respond to the virtual address.
The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer to either a 1 MB
section of physical memory along with attribute information (access permissions, domain, etc.) or an entry in the second level translation
tables; coarse table and fine table.
The second level translation tables contain two subtables, coarse table and fine table. An entry in the coarse table contains a pointer to
both large pages and small pages along with access permissions. An entry in the fine table contains a pointer to large, small and tiny
pages.
Table 7 shows the different attributes of each page in the physical memory.
The MMU consists of:
• Access control logic
• Translation Look-aside Buffer (TLB)
• Translation table walk hardware
10.5.1 Access Control Logic
The access control logic controls access information for every entry in the translation table. The access control logic checks two pieces of
access information: domain and access permissions. The domain is the primary access control mechanism for a memory region; there
are 16 of them. It defines the conditions necessary for an access to proceed. The domain determines whether the access permissions are
used to qualify the access or whether they should be ignored.
The second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. Sections
and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permis-
sions, one for each subpage (quarter of a page).
10.5.2 Translation Look-aside Buffer (TLB)
The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When
the TLB contains an entry for the MVA (Modified Virtual Address), the access control logic determines if the access is permitted and outputs
the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort.
If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation information from
the translation table in physical memory.
10.5.3 Translation Table Walk Hardware
The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address
and access permissions and updates the TLB.
The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access
or a page-mapped access.
Table 10-6: Mapping Details
Mapping Name Mapping Size Access Permission By Subpage Size
Section 1 Mbyte Section –
Large Page 64 Kbytes 4 separated subpages 16 Kbytes
Small Page 4 Kbytes 4 separated subpages 1 Kbyte
Tiny Page 1 Kbyte Tiny Page –