Datasheet

SAM9G20

DS60001516A-page 48  2017 Microchip Technology Inc.

Note 1: Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of

the opcode_2 field.

2: Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field.

10.4.1 CP15 Registers Access

CP15 registers can only be accessed in privileged mode by:

• MCR (Move to Coprocessor from Arm Register) instruction is used to write an Arm register to CP15.

• MRC (Move to Arm Register from Coprocessor) instruction is used to read the value of CP15 to an Arm register.

Other instructions like CDP, LDC, STC can cause an undefined instruction exception.

The assembler code for these instructions is:

MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.

The MCR, MRC instructions bit pattern is shown below:

CRm[3:0]: Specified Coprocessor Action

Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register

behavior.

opcode_2[7:5]

Determines specific coprocessor operation code. By default, set to 0.

Rd[15:12]: Arm Register

Defines the Arm register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable.

CRn[19:16]: Coprocessor Register

Determines the destination coprocessor register.

L: Instruction Bit

0: MCR instruction

1: MRC instruction

opcode_1[23:20]: Coprocessor Code

Defines the coprocessor specific code. Value is c15 for CP15.

cond [31:28]: Condition

For more details, see Chapter 2 in Arm926EJ-S TRM.

13 Context ID

(1)

Read/Write

14 Reserved None

15 Test configuration Read/Write

31 30 29 28 27 26 25 24

cond 1110

23 22 21 20 19 18 17 16

opcode_1 L CRn

15 14 13 12 11 10 9 8

Rd 1111

76543210

opcode_2 1 CRm

Table 10-5: CP15 Registers (Continued)