Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 47
SAM9G20
10.4 CP15 Coprocessor
Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below:
•Arm9EJ-S
• Caches (ICache, DCache and write buffer)
•TCM
•MMU
• Other system options
To control these features, CP15 provides 16 additional registers. See Table 10-5.
LDR Load Word STR Store Word
LDRH Load Half Word STRH Store Half Word
LDRB Load Byte STRB Store Byte
LDRSH Load Signed Halfword LDRSB Load Signed Byte
LDMIA Load Multiple STMIA Store Multiple
PUSH Push Register to stack POP Pop Register from stack
BCC Conditional Branch BKPT Breakpoint
Table 10-5: CP15 Registers
Register Name Read/Write
0 ID Code
(1)
Read/Unpredictable
0 Cache type
(1)
Read/Unpredictable
0 TCM status
(1)
Read/Unpredictable
1 Control Read/Write
2 Translation Table Base Read/Write
3 Domain Access Control Read/Write
4 Reserved None
5 Data fault Status
(1)
Read/Write
5 Instruction fault status
(1)
Read/Write
6 Fault Address Read/Write
7 Cache Operations Read/Write
8 TLB operations Unpredictable/Write
9 cache lockdown
(2)
Read/Write
9 TCM region Read/Write
10 TLB lockdown Read/Write
11 Reserved None
12 Reserved None
13 FCSE PID
(1)
Read/Write
Table 10-4: Thumb Instruction Mnemonic List (Continued)
Mnemonic Operation Mnemonic Operation