Datasheet
SAM9G20
DS60001516A-page 450 2017 Microchip Technology Inc.
The baud rate is calculated with the following formula:
The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%.
31.6.1.3 Fractional Baud Rate in Asynchronous Mode
The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples
of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The gen-
erator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. This fractional part is programmed
with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one
eighth of the clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using
the following formula:
The modified architecture is presented in Figure 31-4.
Figure 31-4: Fractional Baud Rate Generator
25 000 000 38 400 40.69 40 38 109.76 0.76%
32 000 000 38 400 52.08 52 38 461.54 0.16%
32 768 000 38 400 53.33 53 38 641.51 0.63%
33 000 000 38 400 53.71 54 38 194.44 0.54%
40 000 000 38 400 65.10 65 38 461.54 0.16%
50 000 000 38 400 81.38 81 38 580.25 0.47%
Table 31-2: Baud Rate Example (OVER = 0) (Continued)
Source Clock
(MHz)
Expected Baud Rate
(bit/s) Calculation Result CD
Actual Baud Rate
(bit/s) Error
BaudRate MCK CD 16×⁄=
Error 1
ExpectedBaudRate
ActualBaudRate
---------------------------------------------------
–=
Baudrate
SelectedClock
82 Over–()CD
FP
8
-------
+
----------------------------------------------------------------
=
MCK/DIV
16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
Reserved
MCK
SCK
USCLKS
OVER
SCK
SYNC
SYNC
USCLKS = 3
1
0
2
3
0
1
0
1
FIDI
glitch-free
logic
Modulus
Control
FP
FP