Datasheet

SAM9G20
DS60001516A-page 440  2017 Microchip Technology Inc.
30.7.7 TWI Interrupt Enable Register
Name: TWI_IER
Access: Write-only
TXCOMP: Transmission Completed Interrupt Enable
RXRDY: Receive Holding Register Ready Interrupt Enable
TXRDY: Transmit Holding Register Ready Interrupt Enable
SVACC: Slave Access Interrupt Enable
GACC: General Call Access Interrupt Enable
OVRE: Overrun Error Interrupt Enable
NACK: Not Acknowledge Interrupt Enable
ARBLST: Arbitration Lost Interrupt Enable
SCL_WS: Clock Wait State Interrupt Enable
EOSACC: End Of Slave Access Interrupt Enable
ENDRX: End of Receive Buffer Interrupt Enable
ENDTX: End of Transmit Buffer Interrupt Enable
RXBUFF: Receive Buffer Full Interrupt Enable
TXBUFE: Transmit Buffer Empty Interrupt Enable
0: No effect.
1: Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK
76543210
– OVRE GACC SVACC – TXRDY RXRDY TXCOMP