Datasheet

SAM9G20
DS60001516A-page 44  2017 Microchip Technology Inc.
More than one exception can happen at a time, therefore the Arm9EJ-S takes the arisen exceptions according to the following priority
order:
• Reset (highest priority)
• Data Abort
•FIQ
•IRQ
• Prefetch Abort
• BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority)
The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive.
Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the
Arm9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return from the FIQ causes the Data
Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape
detection.
Exception Modes and Handling
Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt from a peripheral.
When handling an Arm exception, the Arm9EJ-S core performs the following operations:
1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode that has been
entered. When the exception entry is from:
- Arm and Jazelle states, the Arm9EJ-S copies the address of the next instruction into LR (current PC(r15) + 4 or PC + 8 depending
on the exception).
- THUMB state, the Arm9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on
the exception) that causes the program to resume from the correct place on return.
2. Copies the CPSR into the appropriate SPSR.
3. Forces the CPSR mode bits to a value that depends on the exception.
4. Forces the PC to fetch the next instruction from the relevant exception vector.
The register r13 is also banked across exception modes to provide each exception handler with private stack pointer.
The Arm9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions.
When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC
and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR.
The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving
which minimizes the overhead of context switching.
The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs,
the Arm9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage
in the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take
place.
The breakpoint (BKPT) instruction is a new feature of Arm9EJ-S that is destined to solve the problem of the Prefetch Abort. A breakpoint
instruction operates as though the instruction caused a Prefetch Abort.
A breakpoint instruction does not cause the Arm9EJ-S to take the Prefetch Abort exception until the instruction reaches the Execute stage
of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not
take place.
10.3.8 Arm Instruction Set Overview
The Arm instruction set is divided into:
• Branch instructions
• Data processing instructions
• Status register transfer instructions
• Load and Store instructions
• Coprocessor instructions
• Exception-generating instructions
Arm instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]).
For further details, see the Arm Technical Reference Manual, Arm ref. DDI0198B.