Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 439
SAM9G20
EOSACC: End Of Slave Access (clear on read)
This bit is only used in Slave mode.
0: A slave access is being performing.
1: The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset.
EOSACC behavior can be seen in Figure 30-29 and Figure 30-30.
ENDRX: End of RX buffer
This bit is only used in Master mode.
0: The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR.
1: The Receive Counter Register has reached 0 since the last write in TWI_RCR or TWI_RNCR.
ENDTX: End of TX buffer
This bit is only used in Master mode.
0: The Transmit Counter Register has not reached 0 since the last write in TWI_TCR or TWI_TNCR.
1: The Transmit Counter Register has reached 0 since the last write in TWI_TCR or TWI_TNCR.
RXBUFF: RX Buffer Full
This bit is only used in Master mode.
0: TWI_RCR or TWI_RNCR have a value other than 0.
1: Both TWI_RCR and TWI_RNCR have a value of 0.
TXBUFE: TX Buffer Empty
This bit is only used in Master mode.
0: TWI_TCR or TWI_TNCR have a value other than 0.
1: Both TWI_TCR and TWI_TNCR have a value of 0.