Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 43
SAM9G20
In all modes and due to a software agreement, register r13 is used as stack pointer.
The use and the function of all the registers described above should obey Arm Procedure Call Standard (APCS) which defines:
• constraints on the use of registers
• stack conventions
• argument passing and result return
For more details, refer to Arm Software Development Kit.
The Thumb state register set is a subset of the Arm state set. The programmer has direct access to:
• Eight general-purpose registers r0–r7
• Stack pointer, SP
• Link register, LR (Arm r14)
•PC
• CPSR
There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the Arm9EJ-S Technical Reference Man-
ual, revision r1p2 page 2-12).
10.3.7.1 Status Registers
The Arm9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers:
• hold information about the most recently performed ALU operation
• control the enabling and disabling of interrupts
• set the processor operation mode
Figure 10-2: Status Register Format
Figure 10-2 shows the status register format, where:
• N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
• The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB,
QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations.
The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the
CPSR. Instructions cannot execute conditionally on the status of the Q flag.
• The J bit in the CPSR indicates when the Arm9EJ-S core is in Jazelle state, where:
- J = 0: The processor is in Arm or Thumb state, depending on the T bit
- J = 1: The processor is in Jazelle state.
• Mode: five bits to encode the current processor mode
10.3.7.2 Exceptions
Exception Types and Priorities
The Arm9EJ-S supports five types of exceptions. Each type drives the Arm9EJ-S in a privileged mode. The types of exceptions are:
• Fast interrupt (FIQ)
• Normal interrupt (IRQ)
• Data and Prefetched aborts (Abort)
• Undefined instruction (Undefined)
• Software interrupt and Reset (Supervisor)
When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state.
NZCVQ JIFT
Mode
Reserved
Mode bits
Thumb state bit
FIQ disable
IRQ disable
Jazelle state bit
Reserved
Sticky Overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
31 3029 2827 24 7 6 5 0