Datasheet

SAM9G20
DS60001516A-page 424  2017 Microchip Technology Inc.
30.6.5 Slave Mode
30.6.5.1 Definition
The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master.
In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are
always provided by the master).
30.6.5.2 Application Block Diagram
Figure 30-23: Slave Mode Typical Application Block Diagram
30.6.5.3 Programming Slave Mode
The following fields must be programmed before entering Slave mode:
1. SADR (TWI_SMR): The slave device address is used in order to be accessed by master devices in read or write mode.
2. MSDIS (TWI_CR): Disable the master mode.
3. SVEN (TWI_CR): Enable the slave mode.
As the device receives the clock, values written in TWI_CWGR are not taken into account.
30.6.5.4 Receiving Data
After a Start or Repeated Start condition is detected and if the address sent by the Master matches with the Slave address programmed
in the SADR (Slave ADdress) field, SVACC (Slave ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer.
SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected, EOSACC (End Of Slave
ACCess) flag is set.
• Read Sequence
In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR (TWI Transmit Holding Register) until a
STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the read sequence
TXCOMP (Transmission Complete) flag is set and SVACC reset.
As soon as data is written in the TWI_THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the shift register is
empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set.
Note that a STOP or a repeated START always follows a NACK.
See Figure 30-24.
• Write Sequence
In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has
been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR.
TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at
the end of the write sequence TXCOMP flag is set and SVACC reset.
See Figure 30-25.
• Clock Synchronization Sequence
In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization.
Host with
TWI
Interface
TWD
TWCK
LCD Controller
Slave 1 Slave 2 Slave 3
RR
VDD
Host with TWI
Interface
Host with TWI
Interface
Master