Datasheet
SAM9G20
DS60001516A-page 42 2017 Microchip Technology Inc.
Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most appli-
cation programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or
exceptions or to access protected resources.
10.3.7 Arm9EJ-S Registers
The Arm9EJ-S core has a total of 37 registers:
• 31 general-purpose 32-bit registers
• Six 32-bit status registers
Table 10-1 shows all the registers in all modes.
The Arm state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Reg-
ister (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values. Register r14 is used as a Link
register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a program counter (PC), whereas
the Current Program Status Register (CPSR) contains condition code flags and the current mode bits.
In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or r13 to r14 in the
other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold
the values (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when BL or BLX instructions are executed
within interrupt or exception routines. There is another register called Saved Program Status Register (SPSR) that becomes available in
privileged modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception
that caused entry to the current (privileged) mode.
Table 10-1: Arm9TDMI Modes and Registers Layout
User and System
Mode Supervisor Mode Abort Mode Undefined Mode Interrupt Mode
Fast Interrupt
Mode
R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
R5 R5 R5 R5 R5 R5
R6 R6 R6 R6 R6 R6
R7 R7 R7 R7 R7 R7
R8 R8 R8 R8 R8
R8_FIQ
R9 R9 R9 R9 R9
R9_FIQ
R10 R10 R10 R10 R10
R10_FIQ
R11 R11 R11 R11 R11
R11_FIQ
R12 R12 R12 R12 R12
R12_FIQ
R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ
R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ
PC PC PC PC PC PC
CPSR CPSR CPSR CPSR CPSR CPSR
SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ
Mode-specific banked registers