Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 415

SAM9G20

• Data Receive with the PDC

1. Initialize the receive PDC (memory pointers, size - 1, etc.).

2. Configure the master mode (DADR, CKDIV, etc.).

3. Start the transfer by setting the PDC RXTEN bit.

4. Wait for the PDC end RX flag.

5. Disable the PDC by setting the PDC RXDIS bit.

30.6.3.8 Read/Write Flowcharts

The flowcharts in the following figures provide examples of read and write operations. A polling or interrupt method can be used to check

the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first.

Figure 30-14: TWI Write Operation with Single Data Byte without Internal Address

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address (DADR)

- Transfer direction bit

Write ==> bit MREAD = 0

Load Transmit register

TWI_THR = Data to send

Read Status register

TXRDY = 1?

Read Status register

TXCOMP = 1?

Transfer finished

Ye s

BEGIN