Datasheet
2017 Microchip Technology Inc. DS60001516A-page 411
SAM9G20
• Multi-master receiver mode
• Slave transmitter mode
• Slave receiver mode
These modes are described in the following sections.
30.6.3 Master Mode
30.6.3.1 Definition
The Master is the device that starts a transfer, generates a clock and stops it.
30.6.3.2 Application Block Diagram
Figure 30-5: Master Mode Typical Application Block Diagram
30.6.3.3 Programming Master Mode
The following registers have to be programmed before entering Master mode:
1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used to access slave devices in read or write mode.
2. CKDIV + CHDIV + CLDIV: Clock Waveform.
3. SVDIS: Disable the slave mode.
4. MSEN: Enable the master mode.
30.6.3.4 Master Transmitter Mode
After the master initiates a Start condition when writing into the Transmit Holding Register, TWI_THR, it sends a 7-bit slave address, con-
figured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the
transfer direction, 0 in this case (MREAD = 0 in TWI_MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th pulse), the master
releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during
this clock pulse and sets the Not Acknowledge bit (NACK) in the status register if the slave does not acknowledge the byte. As with the
other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). If the slave acknowledges the byte,
the data written in the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is detected, the TXRDY bit
is set until a new write in the TWI_THR.
When no more data is written into the TWI_THR, the master generates a stop condition to end the transfer. The end of the complete trans-
fer is marked by the TWI_TXCOMP bit set to one. See Figure 30-6, Figure 30-7, and Figure 30-8.
TXRDY is used as Transmit Ready for the PDC transmit channel.
Host with
TWI
Interface
TWD
TWCK
Microchip TWI
Serial EEPROM
I²C RTC
I²C LCD
Controller
Slave 1 Slave 2 Slave 3
VDD
I²C Temp.
Sensor
Slave 4
Rp: Pull up value as given by the I²C Standard
Rp Rp