Datasheet

SAM9G20
DS60001516A-page 408  2017 Microchip Technology Inc.
30. Two-wire Interface (TWI)
30.1 Overview
The Microchip Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line
with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Microchip Two-wire Interface
bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature
Sensor, to name but a few. The TWI is programmable as a master or a slave with sequential or single-byte access. Multiple master capa-
bility is supported. Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies.
The table below lists the compatibility level of the Microchip Two-wire Interface in Master Mode and a full I2C compatible device.
Note 1: START + b000000001 + Ack + SrQ
30.2 List of Abbreviations
Table 30-1: Microchip TWI compatibility with i2C Standard
I2C Standard Microchip TWI
Standard Mode Speed (100 kHz) Supported
Fast Mode Speed (400 kHz) Supported
7 or 10 bits Slave Addressing Supported
START BYTE
(1)
Not Supported
Repeated Start (Sr) Condition Supported
ACK and NACK Management Supported
Slope control and input filtering (Fast mode) Not Supported
Clock stretching Supported
Table 30-2: Abbreviations
Abbreviation Description
TWI Two-wire Interface
A Acknowledge
NA Non Acknowledge
PStop
SStart
Sr Repeated Start
SADR Slave Address
ADR Any address except SADR
R Read
WWrite